Research Topic Computer Architecture - DRAM Refresh technology mash

Research Topic Computer Architecture – DRAM Refresh

Research Topic Computer Architecture – DRAM Refresh 




Research Topic Computer Architecture – DRAM Refresh. It is a hot topic for research these days. As we explained the functioning of DRAM in a multi core processor system. There were problems faced in queuing the application or prioritizing issues. This is all about the refreshing bits of DRAM Memory Banks to prevent data loss.

Research Topic Computer Architecture - DRAM Refresh technology mash

For all of those who have studied about Capacitor. Once we charge a capacitor the charge does not remain forever even if we do not discharge the capacitor manually. This is due to the charge leakage as nothing is perfect on this earth. Now DRAM Memory banks are made up of capacitors which indicate the value of a bit whether it is 0 or 1. 0 means the capacitor is discharged and 1 means the capacitor is charged. Now as we all know from the previous post that the application data is loaded into DRAM Memory Banks and the one row which needs to be accessed instantly is loaded into Memory Row Buffer. Now due to charge leakage, any of the capacitors can lose its charge and change the bit from 1 to 0.

We already have a redundant bit to solve this problem if only one of the bits is lost but, what if multiple bits are lost.

Research Topic Computer Architecture – DRAM Refresh 

To solve these kinds of problems due to the quality and efficiency of the capacitor, We found a new way to refresh each capacitor. We take base time in which the capacitor would not lose the whole of its charge and refresh the charge of all capacitor within that time. Now the problem is the setting of time, What should be the time set for DRAM refresh as different Make of DRAM’s have different quality of Capacitors and Time of Retention of charge will be different for them. So the computer industry has set a standard for quality of capacitor that a capacitor should at least store a charge for 64ms which is currently the DRAM Refresh time. After this time each capacitor in DRAM Memory Bank is refreshed which takes up a lot of Power. Earlier the DRAM sizes were less but nowadays as the DRAM Memory sizes are doubling every year the power consumed will also be doubled along with time wasted in the refresh.

technology mash dram refresh

According to a Research Paper written by  Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, and Onur Mutlu. DRAM Refresh time and power can be reduced by using Bloom Filters and analyzing which rows needs to be refreshed. Earlier we were refreshing each bit and now a whole row is refreshed and no of bits to store info on which rows need to be refreshed is reduced which may not be completely efficient but better than what we use now.

A completely efficient way to do this would be to break the abstraction layers and initiate the refreshing from OS level. OS tells the DRAM which data would be required for further processing of Applications and only those rows required are refreshed.

Research Topic Computer Architecture – DRAM Refresh 

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