2 Hot Topics to Publish your Research Paper on Computer Architecture - DRAM technology mash

Hot Topics to Publish your Research Paper on Computer Architecture – DRAM

Hot Topic to Publish your Research Paper on Computer Architecture – DRAM




Hot Topics to Publish your Research Paper on Computer Architecture – DRAM

Hot Topics to Publish your Research Paper on Computer Architecture – DRAM

I am going to start with Processors, We shifted from single core to multi core many years ago. You won’t find even a Single Core processor computer at present time.

2 Hot Topics to Publish your Research Paper on Computer Architecture - DRAM technology mash

Single core processors had one processor which could perform only one process at a time but the switching between the processes was so fast that It gave an illusion of multi tasking. Later the innovators switched to Multi core processors, which consisted of multi processors and also supported multi tasking. Now as multi cores came into existence, We mainly started focusing on the power and count of cores. We started optimizing things at the processor level. After shifting to the multi core systems, Some problems came up which were unnoticed. As we gradually increased the processing power over years, we forgot some things about memory. Now as we know there are multiple processes running on different cores which are in turn connected to a DRAM Memory Controller. DRAM Memory Controller further has divisions called DRAM Bank. All the applications share the same DRAM Controller.

DRAM controller is a type of 2D matrix of memory with rows and columns. For each DRAM Bank, a row is added to memory buffer which provides instant and super quick access to the data for an application.

For example, there are two programs Program A and Program B

Requirement

Program A – Has to access data from just one row in DRAM Bank which is loaded initially into Buffer e.g Row 4.

Program B – Has to access data from multiple rows in DRAM Bank, one of which can be loaded into Buffer at a time e.g Row 2, 79, 654, etc.

Output when ran on Single Core

Program A – 130 seconds

Program A – 40 seconds

Output when ran on Multi Cores 

Program A – 139 seconds

Program A – 200 seconds

 

This is because in multi core we have to assign priority to one task for accessing DRAM Bank as there are multiple processing going on at the same time. Currently, we give priority to the application which requests to access the Row already present in Row Buffer. This is really a good topic to get your hands on. For more info Follow CSAPP CMU below.

DRAM Priority Issue still needs new ideas and can be researched easily.

 

Hot Topic to Publish your Research Paper on Computer Architecture – DRAM

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